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inch-pound mil-m-38510/210e 27 march 2006 superseding mil-m-38510/210d 16 may 1986 military specification microcircuit, digital, 16, 384 bit schottky, bipolar, programm able read-only memory (prom), monolithic silicon this specification is approved for use by all departments and agencies of the department of defense. the requirements for acquiring the product herein shall consist of this specificat ion sheet and mil-prf 38535. 1. scope 1.1 scope. this specification covers the detail requirements for monolithic silicon, programmable read-only memory (prom) microcircuits which employ thin film nichrome (nicr) re sistors, platinum-silicide, t ungsten (w), titanium-tungsten (tiw) or zapped vertical emitter as the fusible link or progr amming element. two product assurance classes and a choice of case outlines and lead finishes are provided and are reflect ed in the complete part number. for this product, the requirements of mil-m-38510 have been su perseded by mil-prf-38535, (see 6.4). 1.2 part or identifying number (pin). the pin is in accordance with mi l-prf-38535, and as specified herein. 1.2.1 device types. the device types are as follows: device type circuit access times (ns) 01 2048 words/8 bits per word prom with uncommitted 100, 50 collector 02 2048 words/8 bits per word prom with active pull-up 100, 50 and a third high-impedance state output 03 2048 words/8 bits per word prom with unco mmitted 55, 30 collector 04 2048 words/8 bits per word prom with active pull-up 55, 30 and a third high-impedance state output 05 4096 words/4 bits per word prom with active pull-up 80, 40 and a third high-impedance state output 1.2.2 device class. the device class is the product assurance level as defined in mil-prf-38535. 1.2.3 case outlines. the case outlines are as designated in mil-std-1835 and as follows: outline letter descriptive designator terminals package style j gdip1-t24 or cdip2-t24 24 dual-in-line k gdfp2-f24 or cdfp3-f24 24 flat pack r gdip1-t20 or cdip2-t20 20 dual-in-line l gdip3-t24 or cdip4-t24 24 dual-in-line 3 cqcc1-n28 28 square leadless chip carrier comments, suggestions, or questions on this docum ent should be addressed to: commander, defense supply center columbus, attn: dscc-vas, p. o. box 3990, columbus, oh 43218-3990, or emailed to mailto:memory@dla.mil . since contact information can change, y ou may want to verify the currency of this address information using the assist online database at http://assist.daps.dla.mil amsc n/a fsc 5962 inactive for new design after 24 july 1995
mil-m-38510/210e 2 1.3 absolute maximum ratings. supply voltage r ange ............................................................................. -0.5 v dc to +7.0 v dc input voltage range ................................................................................ -1.5 v dc at -10 ma to +5. 5 v dc storage temperatur e range .................................................................... -65 c to +150 c lead temperature (soldering, 10 se conds).............................................. +300 c thermal resistance, junction to case ( jc ): 1 / cases j, l, and r.............................................................................. 40 c/w maximum case k ............................................................................................. 60 c/w maximum case 3 .............................................................................................. 0.08 c/w maximum 2 / output voltage range............................................................................... -0.5 v dc to +v cc output sink cu rrent.................................................................................. 100 ma maximum power dissipation (p d ) 3 / ....................................................... 1.02 w maximum,unction temperature (t j ) 4 / .................................................... +175 c 1.4 recommended operating conditions. supply voltage ....................................................................................... +4 .5 v dc minimum to +5.5 v dc maximum minimum high-level input voltage (v ih ) ................................................... 2. 0 v dc maximum low-level input voltage (v il ) .................................................... 0. 8 v dc normalized fanout (each outp ut) .......................................................... 8 ma 5 / case operating temperature range (t c ) .................................................. -55 c to +125 c 2. applicable documents 2.1 general. the documents listed in this section are specified in sections 3, 4, or 5 of th is specification. this section does not include documents cited in other sectio ns of this specification or recommended for additional information or as examples. while every effort has bee n made to ensure the completeness of this list, document users are cautioned that they must m eet all specified requirements of document s cited in sections 3, 4, or 5 of this specification, whether or not they are listed. 2.2 government documents . 2.2.1 specificat ions and standards . the following specifications a nd standards form a part of this specification to the extent specified herein. unless ot herwise specified, the issu es of these documents are those cited in the solicitation or contract. department of defe nse specifications mil-prf-38535 - integrated circuits (microcircu its) manufacturing, gener al specification for. department of defense standards mil-std-883 - test method standard for microelectronics. mil-std-1835 - interface standard el ectronic component case outline ______ 1 / heat sinking is recommended to reduce the junction temperature. 2 / when a thermal resistance value is included in mi l-std-1835, it shall supers ede the value stated herein. 3 / must withstand the added p d due to short circuit test (e.g. i os ). 4 / maximum junction temperature shall not be exceeded except for allowable short circuit duration burn-in screening conditions per method 5004 of mil-std-883. 5 / 16 ma for circuits a, b, d, f, h, and i devices.
mil-m-38510/210e 3 (copies of these documents are available online at http://assist.daps.dla .mil/quicksearch/ or http://assist.daps.dla.mil or from the standardization document or der desk, 700 robbins avenue, building 4d, philadelphia, pa 19111-5094.) 2.3 order of precedence. in the event of a conflict between the text of this specification and the references cited herein, the text of this document takes preced ence. nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. requirements 3.1 qualification . microcircuits furnished under this specificati on shall be products that are manufactured by a manufacturer authorized by the qualifying activity for listi ng on the applicable qualifie d manufacturers list before contract award (see 4.3 and 6.3). 3.2 item requirements . the individual item requirements shall be in accordance with mil-prf-38535 and as specified herein or as modified in the device manufacturer?s quality management (qm) plan. the modification in the qm plan shall not affect t he form, fit, or function as described herein. 3.3 design, construction, and physical dimensions. the design, construction, and physical dimensions shall be as specified in mil-prf-38535 and herein. 3.3.1 terminal connections. the terminal connections shall be as specified on figure 1. 3.3.2 truth table 3.3.2.1 unprogrammed devices. the truth table for unprogrammed devices for contracts involving no altered itme drawing shall be as specified on figure 2. when requir ed in groups a, b, or c (s ee 4.4), the devices shall be programmed by the manufacturer prior to test in a checke rboard pattern (a minimum of 50 percent of the total number of bits programmed) or to any altered item drawi ng pattern which includes at least 25 percent of the total number of bits programmed. 3.3.2.2 programmed devices. the truth table for programmed devices shall be as specified by the altered item drawing. 3.3.3 functional block diagram . the functional block diagram shall be as specified on figure 3. 3.3.4 case outlines. the case outlines shall be as specified in 1.2.3. 3.4 lead material and finish. the lead material and finish shall be in accordance with mil - prf-38535 (see 6.6). 3.5 electrical performance characteristics . the electrical performance characteristics are as specified in table i, and apply over the full recommended case operat ing temperature range, unl ess otherwise specified. 3.6 electrical test requirements. the electrical test requirements s hall be as specified in table ii, and where applicable, the altered item drawing. the electrical tests for eac h subgroup are descri bed in table iii. 3.7 marking. marking shall be in accordance with mil-prf-38535.
mil-m-38510/210e 4 table i . electrical performance characteristics . limits test symbol conditions 1 / -55 c t c +125 c device type min max unit high-level output voltage v oh v cc = 4.5 v; i oh = -2 ma; v ih = 2.0 v; v il = 0.8 v 02,04,05 2.4 v low-level output voltage v ol v cc = 4.5 v; i ol = 8 ma; 2 / v ih = 2.0 v; v il = 0.8 v 01,02 03,04,05 0.5 v input clamp voltage v ic v cc = 4.5 v; i in = -10 ma; t c = 25 c 01,02 03,04,05 -1.5 v maximum collec tor cut-off current i cex v cc = 5.5 v; v o = 5.2 v 01,03 100 a high-impedance (off-state) output high current i ohz v cc = 5.5 v; v 0 = 5.2 v 02,04,05 100 a high-impedance (off-state) output low current i olz v cc = 5.5 v; v 0 = 0.5 v 02,04,05 -100 a high-level input current i ih v cc = 5.5 v; v in = 5.5 v 01,02 03,04,05 50 a low-level input current i il v cc = 5.5 v; v in = 0.5 v 01,02 03,04,05 -250 a short circuit output current i os v cc = 5.5 v; v 0 = 0.0 v 3 / 02,04,05 -10 -100 ma supply current i cc v cc = 5.5 v; v in = 0; outputs = open 01,02 03,04,05 185 ma 01,02 100 03,04 55 propagation delay time, high-to-low level logic, address to output t phl1 05 80 ns 01,02 100 03,04 55 propagation delay time, low-to-high level logic, address to output t plh1 05 80 ns 01,02 50 03,04 30 propagation delay time, high-to-low level logic, enable to output t phl2 v cc = 4.5 v and 5.5 v; c l = 30 pf (see figure 4) 05 40 ns 01,02 50 03,04 30 propagation delay time, low-to-high level logic, enable to output t plh2 05 40 ns 1 / complete terminal conditions shall be specified in table iii. 2 / i ol = 16 ma for circuits a, b, d, f, h, i, and j. 3 / not more than one output shall be grounded at one time . output shall be at high logic level prior to test.
mil-m-38510/210e 5 table ii. electrical test requirements. subgroups (see table iii) 1 /, 2 /, 3 / mil-prf-38535 test requirements class s devices class b devices interim electrical parameters 1 1 final electrical test parameters for unprogrammed devices 1*, 2, 3, 7*, 8 1*, 2, 3, 7*, 8 final electrical test parameters for programmed devices 1*, 2, 3, 7* 8, 9, 10, 11 1*, 2, 3, 7*, 8, 9, group a test requirements 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8 9, 10, 11 group b end-point electrical parameters subgroup 5 1, 2, 3, 7, 8, 9, 10, 11 n/a group c end-point electrical parameters 1, 2, 3, 7, 8, 9, 10, 11 1, 2, 3, 7, 8 group d test requirements 1, 2, 3, 7, 8 1, 2, 3, 7, 8 1 / * pda applies to subgroups 1 and 7. 2 / any or all subgroups may be combined when using high-speed testers. 3 / subgroups 7 and 8 shall consist of verifying the pattern specified. 3.8 processing options . since the prom is an unprogrammed memory capable of being programmed by either the manufacturer or the user to result in a wi de variety of configurations, two processing options are provided for selection in the contra ct, using an altered item drawing. 3.8.1 unprogrammed prom delivered to the user . all testing shall be verified through group a testing as defined in 3.3.2.1, table ii, and table iii. it is recommended that users perform subgroups 7 and 9 after programming to verify the specific program configuration. 3.8.2 maunufacturer-programmed prom delivered to the user . all testing requirements and quality assurance provisions herein, includi ng the requirements of the altered item drawing, shall be satisfied by the manufacturer prior to delivery. 3.9 microcircuit group assignment. the devices covered by this specif ication shall be in microcircuit group number 14 (see appendix a mil-prf-38535.)
mil-m-38510/210e 6 4. verification 4.1 sampling and inspection. sampling and inspection procedures shall be in accordance with mil-prf- 38535 or as modified in the device manufacturer's qua lity management (qm) plan. the modification in the qm plan shall not effect the form, fi t, or function as described herein. 4.2 screening. screening shall be in accordance with mil-prf-38535 and shall be conducted on all devices prior to qualification and quality co nformance inspection. the following additional criteria shall apply: a. the burn-in test duration, test condition, and test temperature, or approved alternatives shall be as specified in the device manufacturer's qm plan in a ccordance with mil-prf-38535. the burn-in test circuit shall be maintained under document control by the device manufacturer's technology review board (trb) in accordance with mil-prf-38535 and shall be made available to the acquiring or preparing activity upon request. the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of mil-std- 883. b. interim and final electrical test parameters shall be as specified in table ii, ex cept interim electrical parameters test prior to burn-in is optiona l at the discretion of the manufacturer. c. additional screening for space le vel product shall be as specifie d in mil-prf-38535, appendix b. d. class b devices processed to an altered item dr awing may be programmed either before or after burn-in at the manufacturer?s di scretion. the required electrical testing shall include, as a minimum, the final electrical tests for programm ed devices as specified in table ii herein. class s devices processed by the manufacturer to an altere d item drawing shall be programmed prior to burn- in. 4.3 qualification inspection. qualification inspection shall be in accordance with mil-prf-38535. 4.4 technology conformance inspection (tci). technology conformance inspection shall be in accordance with mil-prf-38535 and as specified herein for groups a, b, c, and d inspections (see 4.4.1 through 4.4.4). 4.4.1 group a inspection. group a inspection shall be in accordan ce with table iii of mil-prf-38535 and as follows: a. electrical test requirements sha ll be as specified in table ii herein. b. subgroups 4, 5, and 6 shall be omitted. c. for unprogrammed devices, a sample shall be be selected to satisfy programmability requirements prior to performing subgroups 9, 10, and 11. twelve devices shall be submitted to programming (see 3.3.2.1). if more than 2 devices fail to program, the lot shall be rejected, at the manufacturer?s option, the sample may be increased to 24 total devices with no more than 4 total device failures allowed. d. for unprogrammed devices, 10 devices from the programmability sample shall be submitted to the requirements of group a, subgroups 9, 10, and 11. if more than two total devices fail in all three subgroups, the lot shall be rejected. at the manufac turer?s option, the sample may be increased to 20 total devices with no more that 4 total device failures allowed.
mil-m-38510/210e 7 4.4.2 group c inspection. group c inspection shall be in accordance with table iv of mil-prf-38535 and as follows: a. end-point electrical parameters shall be as specified in table ii herein. b. the steady-state life test duration, test condition, and test temperat ure, or approved alternatives shall be as specified in the device manufacturer's qm pl an in accordance with mil-prf-38535. the burn- in test circuit shall be maintained under document control by the device manufacturer's technology review board (trb) in accordance with mil-prf-38535 and shall be made available to the acquiring or preparing activity upon request. the test circ uit shall specify the input s, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005 of mil- std-883. c. for qualification, at least 50 percent of the sample selected for testing in subgroup 1 shall be programmed (see 3.3.2). for quality conformance inspection, the programmability sample (see 4.4.1c) shall be included in the subgroup 1 tests. 4.4.3 group d inspection. group d inspection shall be in accordance with table v of mil-prf-38535. end- point electrical parameters shall be as specified in table ii herein. 4.5 methods of inspection. methods of inspection shall be specified and as follows: 4.5.1 voltage and current. all voltages given are referenced to the microcircuit ground terminal. currents given are conventional and positive when flowing into the referenced terminal. 4.6 programming proce dure identification. the programming procedure to be utilized shall be identified by the manufacturer?s circuit designator. the circuit des ignator is cross referenced in 6.5 herein with the manufacturer?s symbol.
mil-m-38510/210e 8 4.7 programming procedure for circuit a . the programming characteristics of table iva and the following procedures shall be used for programming the device. a. connect the device in the electrical configur ation for programming. the waveforms on figure 5a and the programming characteristics of table iva shall apply to these procedures. b. address the prom with the binary address of the selected word to be programmed. address inputs are ttl compatible. an open circuit shall not be used to address the prom. c. apply v pl voltage to v cc . d. bring the ce x inputs high and the ce x inputs low to disable the device. the chip enables are ttl compatible. an open circuit shall not be used to disable the device. e. disable the programming circuitry by applying a voltage of v opd to the outputs of the prom. f. raise v cc to v ph with rise time less than or equal to t tlh . g. after a delay equal to or greater than t d1 , apply only one pulse with amplitude of v ope and duration of t p to the output selected for programming. note that the prom is supplied with fuses intact, which generates an output high. programming a fuse will cause the output to go low. h. lower v cc to v pl following a delay of t d2 from programming enable pulse applied to an output. i. enable the prom fo r verification by applying v il to ce x and v ih to ce x . j. apply v phv to v cc and verify bit is programmed. k. repeat 4.7a through 4.7j for all ot her bits to be programmed in the prom. l. if any bit does not verify as programmed, it shall be considered a programming reject. 4.8 programming procedure for circuit b . the programming characteristics of table ivb and the following procedures shall be used for programming the device. a. connect the device in the electrical configur ation for programming. the waveforms on figure 5b and the programming characteristics of table ivb shall apply to these procedures. b. apply v ih ce 1 and the binary address of the prom word to be programmed. raise v cc to v ccp . c. after a t d delay, apply only one v op to the output to be programmed high. apply v op to one output at a time. d. after a t d delay, a pulse ce 1 to a v il level for a duration of t p . e. after t p and a t d delay, remove v op from the programmed output. f. other bits in the same word may be programmed sequentially while the v cc input is at the v ccp level by applying v op pulses to each output to be programmed and pulsing ce 1 to the v il level, allowing for proper delays between v op and ce 1 . g. repeat 4.8b through 4.8e fo r all bits to be programmed. h. to verify programming, lower v ccp to v cc . connect a 10 k ? resistor between each output and v cc . apply v il to ce 1 input. the programmed outputs should remain in the high state and the unprogrammed outputs should go to the low level.
mil-m-38510/210e 9 i. if any bit does not verify as programm ed, it shall be considered a programming reject. 4.9 programming procedures for circuit c, device types 02 and 04 . the programming characteristics of table ivc and the following procedures shall be used for programming device types 02 and 04. a. connect the device in the el ectrical configuration for programming. the waveforms on figure 5c, device types 02 and 04, and the programming characteristics of table ivc, device types 02 and 04, shall apply to these procedures. b. terminate all device outputs with a 10 k ? resistor to v cc . apply v ih to ce 1 . c. address the prom with the binary address of the selected word to be programmed. raise v cc to v ccp . d. after a t d delay (10 s), apply only one v out pulse to the output to be programmed. program one output at a time. e. after a t d delay (10 s), pulse ce 1 input to logic ?0? for a duration of t p . f. after a t d delay (10 s), remove the v out pulse from the programmed output. (programming a fuse will cause the output to go to a high-level logic in the verify mode.) g. other bits in the same word may be programmed sequentially while the v cc input is at the v ccp level by applying v out pulses to each output to be programmed allowing a delay to t d between pulses as shown on figure 5c. h. repeat 4.9b through 4.9g for all other bits to be programmed. i. to verify programming, after t d (10 s) delay, lower v cc to v cch and apply a logic ?0? level to ce 1 input. the programmed output should remain in the ?1? state. again, lower v cc to v ccl and verify that the programmed output remain s in the ?1? state. j. if any bit does not verify as programmed, it shall be considered a programming reject. 4.10 programming procedures for circuit c, device type 05 . the programming characteristics of table ivc, device type 05, and the following procedures shall be used for programming the device. a. connect the device in the elec trical configuration for programming. the output pins shall be terminated with a 10 k ? resistor to gnd and bypass vcc to gnd with a 0.01 f capacitor. the waveforms on figure 5c, device type 05, and the programming characte ristics of table ivc, dev ice type 05, shall apply to these procedures. b. disable the device by applying v ih to ce 2 input and v il to ce 1 . the chip enable pins are ttl compatible. c. apply v il to all other pins. d. address the prom with the binary address of the selected word to be programmed and reset t p = 5 s. address inputs are ttl compatible. e. after a delay of td 1 , raise the v cc pin to v ccp . f. after a delay of td 2 , raise the corresponding output pin to v opf . g. after a delay of td 3 , lower ce 2 to v il for a duration of t p and simultaneously lower the output to v il and wait td 4 .
mil-m-38510/210e 10 h. return the ce 2 to v ih . i. wait td 5 and lower v cc to v ccv . j. wait td 6 and lower ce 2 to v il for the duration to t v . k. a properly blown fuse will read vol and unblown fuse will read voh. 1. if the fuse is blown, go to n. 2. if the fuse is unblown, go to 1. l. if t p is less than 30 s, increment t p by 5 s and go to e. if t p is 5 s go to m. m. if t p is 30 s, the device is a reject. n. after a delay of td 7 , select the next output or address to be programmed. o. repeat steps 4.10d through 4.10k unt il all required addresses are programmed. p. to verify the program keep v cc pin at v ccv . apply v il to ce 2 . the programmed fuse will go to the low level and unblown fuse shall remain in the high level. 4.11 programming procedures for circuit d . the programming characteristics on table ivd, and the following procedures shall be used for programming the device. a. connect the device in the electrical configur ation for programming. the waveforms on figure 5d and the programming characteristics of table ivd shall apply to these procedures. b. select the word to be programmed by applying the appropriate voltages to the address pins as well as the required voltages to chip enable pins to select the device. c. apply the proper power, v cc = 6.5 v, gnd = 0 v. d. verify that the bit to be prog rammed is in the ?0? logic state. e. enable the chip for programming by application of the chip enable voltage, v p(ce1) = 21.0 v to ce 1 (pin 20). ce 2 and ce 3 should be left high. f. apply i op programming current ramp to the output to be programmed. the other outputs shall be left open. only one output may be programmed at a time. during the rise of the current ramp, the required current will be achieved to program the junction. as programming occurs a drop in voltage can be sensed at the output of the device. upon detection of v ps , the current shall be held for t hap and then shut off. g. verify that the programmed bit is in the ?1? logic state. lower v p(ce1) to 0 v and read the output. note: the prom is supplied with fuses generating a low-level logic output. programming a fuse will cause the output to go to a high-level logic in the verify mode. h. lower v cc to 0 v. the power supply duty cycle shall be equal to or less than 50 percent. i. if the bit verifies as not having been programmed at v cc = 6.5 v, then repeat the programming ramp sequence up to 15 times until the bit is programmed. if after 16 programming attempts, the bit does not program, then the device shall be considered a reject.
mil-m-38510/210e 11 j. if the bit verifies as having been programmed at v cc = 6.5 v, then one of the following two conditions shall be followed: (1) if the cu rrent required to program was less than i op(max) , then proceed to step 1. (2) if the current required to program was equal to or greater than iop(max), then the device shall be considered a reject and no further attempts at programmi ng other bits shall be attempted. k. repeat 4.11a through 4.11j for all other bits to be programmed. l. if any bit does not verify as programmed, it shall be considered a programming reject. 4.12 programming procedures for circuit e . the programming characteristics for this device have been discontinued. 4.13 programming procedures for circuit f . the programming characteristics on table ivf and the following procedures shall be used for programming the devices: a. connect the device in the electrical configur ation for programming. the waveforms on figure 5f and the programming characteristics of table ivf shall apply to these procedures. b. raise v cc to 5.5 v. c. address the prom with binary address of the selected word to be programmed. address inputs are ttl compatible. d. disable the chip by applying v ih to the ce inputs and v il to the ce inputs. the chip enable inputs are ttl compatible. e. apply the v pp pulse to the programming pin ce 1 . in order to insure that the output transistor is off before increasing voltage on the out put pin, the program pins volt age pulse shall precede the output pins programming pulse by t d1 and leave after the programming pins programming pulse by t d2 (see figure 5f). f. apply one v out pulse with duration of t p to the output selected for pr ogramming. the outputs shall be programmed one output at a time, since internal decoding circuitry is capable of sinking only one unit of programming current at a time. note: the prom is supplied with fuses generati ng a high-level logic output. programming a fuse will cause the output to go to a low-level logic in the verify mode. g. other bits in the same word may be programmed sequentially by applying v out pulses to each output to be programmed. h. repeat 4.13b through 4.13g fo r all other bits to be programmed. i. enable the chip by applying v il to the ce inputs and v ih to the ce inputs, and verify the program. verification may check for a low output by requiring the device to sink 12 ma at v cc = 4.2 v and 0.2 ma at v cc = 6.2 v at t c = 25 c. j. if any bit does not verify as programm ed, it shall be considered a programming reject.
mil-m-38510/210e 12 4.14 programming procedures for circuit g . the programming characteristics on table ivg and the following procedures shall be used for programming the devices: a. connect the device in the electrical configur ation for programming. the waveforms on figure 5g and the programming characteristics of table ivg shall apply to these procedures. b. select the desired word by applying high or lo w levels to the appropriate address inputs. disable the device by applying a high level to one or more ?active low? chip enable inputs. note: address and enable inputs must be driven with ttl logic levels during programming and verification. c. increase v cc from nominal to v ccp (10.5 0.5 v) with a slew rate limit of i rr (1.0 to 10.0 v/ s). since v cc is the source of the current required to program the fuse as well as the i cc for the device at the programming voltage, it must be capa ble of supplying 750 ma at 11.0 v. d. select the output where a logical high is desired by raising that output voltage to v op (10.5 0.5 v). limit the slew rates to i rr (1.0 to 10.0 v/ s). this voltage change may occur simultaneously with the v cc increase to v ccp , but must not precede it. it is critical that only one output at a time be programmed since the internal circuits can only supply programmi ng current to one bit at a time. outputs not being programmed must be left open or connected to a high impedance source of 20 k ? minimum (remember that the outputs of the device are disabled at this time). e. enable the device by taking the chip enable(s) to a low level. this is done with a pulse pwe for 10 s. the 10 s duration refers to the time that the circuit ( device) is enabled. normal input levels are used and rise and fall times are not critical. f. verify that the bit has been programmed by firs t removing the programming voltage from the output and then reducing v cc to 5.0 v ( 0.25 v). the device must be enabled to sense the state of the outputs. during verification, the loading of the output must be within specified i ol and i oh limits. g. if the device is not to be tested for v oh over the entire temperature ra nge subsequent to programming, the verification of step 4.14f is to be performed at a v cc level of 4.0 v ( 0.2 v). v oh , during the 4 v verification, must be at least 2.0 v. the 4 v v cc verification assures minimum v oh levels over the entire temperature range. h. repeat 4.14b through 4.14f for each bit to be pr ogrammed to a high level. if the procedure is performed on an automatic programmer, the duty cycle of vcc at the programming voltage must be limited to a maximum of 25 percent. this is necessary to minimi ze device junction temperatures. after all selected bits are programmed, the entire content s of the memory should be verified. i. if any bit does not verify as programm ed, it shall be considered a programming reject.
mil-m-38510/210e 13 4.15 programming procedures for circuit h . the programming characteristics of table ivh and the following procedures shall be used for programming the device. a. connect the device in the electrical configur ation for programming. the waveforms on figure 5h and the programming characteristics of table ivh shall apply to these procedures. b. address the word to be programmed, apply 5 v to v cc and active levels to all chip enable inputs. c. verify the status of a bit location by checking the output level. d. decrease v cc to 0 v. e. for bit locations that do not require programming, skip steps 4.15f through 4.15l. f. increase v cc to v cc(pr) with a minimum current capability of 250 ma. g. apply v s(pr) to all chip en able inputs. i i 25 ma. active-high enables may be left high. h. connect all outputs, except the one to be programmed, to v il . only one bit is to be programmed at a time. i. apply the output programming pulse for 20 s. minimum current capability of the programming supply should be 250 ma. j. after terminating the output pu lse, disconnect all outputs from v il conditions. k. reduce the voltage at ce input to v il . l. decrease v cc to 0 v. m. return to 4.15e until all outputs in the word have been programmed. n. repeat 4.15c through 4.15l for each word in memory. o. verify programming of every word after all words have been programmed using v cc values of 4.5 v and 5.5 v. p. if any bit does not verify as programmed, it shall be considered a programming reject. 4.16 programming procedures for circuit i . the programming characteristics in table ivi and the following procedures shall be used for programming the device: a. connect the device in the el ectrical configuration for programmi ng. the waveforms on figure 5i and the programming characteristics of table ivi shall apply to these procedures. b. terminate all outputs with a 300 ? resistor to v onp . apply v ihp to the ce 2 , ce 3 , and ce 4 inputs and v ilp to the ce 1 inputs. c. address the prom with the binary address of the selected word to be programmed. raise v cc to v ccp . d. after a delay of t 1 , apply only one v op pulse with a duration of t p , t 2 and d(v op )/dt to the output selected for programming. after a delay of t 2 and d(v op )/dt, pulse ce 2 from v ihp to v cep for the duration of t p , 2d(v ce )/dt, and t 3 ; ce 2 is then to go to v ilp level. e. to verify programming after ce 1 has been set to v ilp , lower v cc to v ccl after a delay of t 4 . the programmed output should remain in the logic ?1? state.
mil-m-38510/210e 14 f. the outputs should be programmed one output at a time, since the internal decoding circuitry is capable of sinking only one unit of programming current at a time. note that the prom is supplied with fuses generating a low-level logic output. programming a fuse will cause the output to go to a high level logic in the verify mode. g. repeat 4.16b through 4.16f for all other bits to be programmed. h. if any bit does not verify as programm ed, it shall be considered a programming reject. 4.17 programming procedures for circuit j . the programming characteristics in table ivj and the following procedures shall be used for programming the device: a. connect the device in the el ectrical configuration for programming. the waveforms on figure 5j and the programming characteristics of table ivj shall apply to these procedures. b. address the prom with the binary address of the selected word to be programmed. address inputs are ttl compatible. an open circuit should not be used to address the prom. c. disable the chip by applying input high (v ih ) to the cs input. cs input must remain at v ih for programming. the chip select is ttl compatible. an open circuit should not be used to disable the chip. d. disable the programming circuitry by applying an output voltage disable of less than v opd to the output of the prom. the output may be le ft open to achieve the disable. e. raise v cc to v ph with rise time equal to t r . f. after a delay equal to or greater than t d , apply a pulse with amplitude of v ope and duration of t p to the output selected for programming. note that the prom is supplied with fuses intact generating an output high. programming a fuse will cause the output to go low in the verify mode. g. other bits in the same word may be programmed while the v cc input is raised to v ph by applying output enable pulses to each output which is to be progr ammed. the output enable pulses must be separated by a minimum interval of t d . h. lower v cc to 4.5 v following a delay of t d from the last programming enable pulse applied to an output. i. enable the prom for verification by applying a logic ?0? (v il ) to the cs input. j. repeat 4.17a through 4.17i for a ll other bit to be programmed in the prom. k. if any bit does not verify as programmed, it shall be considered a programming reject.
mil-m-38510/210e 15 device type 01, 02, 03, 04 05 02 and 04 case outline j, k, and l r 3 terminal number terminal symbol 1 a7 a8 nc 2 a6 a7 a7 3 a5 a6 a6 4 a4 a5 a5 5 a3 a4 a4 6 a2 a3 a3 7 a1 a2 a2 8 a0 a1 a1 9 o1 a0 a0 10 o2 gnd nc 11 o3 o4 o1 12 gnd o3 o2 13 o4 o2 o3 14 o5 o1 gnd 15 o6 ce 2 nc 16 o7 ce 1 o4 17 o8 a11 o5 18 ce 3 a10 o6 19 ce 2 a9 o7 20 ce 1 v cc o8 21 a10 ---- nc 22 a9 ---- ce 3 23 a8 ---- ce 2 24 v cc ---- ce 1 25 ---- ---- a10 26 ---- ---- a9 27 ---- ---- a8 28 ---- ---- v cc figure 1. terminal connections.
mil-m-38510/210e 16 device types 01, 02, 03, and 04 6 / 6 / 6 / address data word no. ce 1 ce 2 ce 3 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o8 o7 o6 o5 o4 o3 o2 o1 na l h h x x x x x x x x x x x 5 /5 / 5 / 5 / 5 / 5 / 5 / 5 / na h x x x x x x x x x x x x x oc oc oc oc oc oc oc oc device type 05 6 / 6 / address data word no. ce 1 ce 2 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 o4 o3 o2 o1 na l l x x x x x x x x x x x x 5 / 5 / 5 / 5 / na h x x x x x x x x x x x x x oc oc oc oc notes: 1. na = not applicable. 2. x = input may be high level, low level, or open circuit. 3. oc = open circuit (high resistance output). 4. program readout can only be accomplis hed with enable input at low level. 5. the outputs for an unprogrammed device shall be hi gh for circuits a, c, (device type 05), e, f, and j and low for circuits b, c (device types 02, 04), d, g, and i. 6. enable inputs are anded. figure 2. truth table (unprogrammed).
mil-m-38510/210e 17 device types 01 and 02 circuit a figure 3. functional block diagrams .
mil-m-38510/210e 18 device type 05 circuit a figure 3. functional block diagrams ? continued.
mil-m-38510/210e 19 device types 01 and 02 circuit b figure 3. functional block diagram ? continued.
mil-m-38510/210e 20 device types 01, 02, and 04 circuit c figure 3. functional block diagrams ? continued.
mil-m-38510/210e 21 device type 05 circuit c figure 3. functional block diagrams - continued
mil-m-38510/210e 22 device types 02, 03, and 04 circuit d figure 3. functional block diagrams ? continued.
mil-m-38510/210e 23 device type 02 circuits f and i figure 3. functional block diagrams ? continued.
mil-m-38510/210e 24 device type 01 circuit g figure 3. functional block diagrams ? continued.
mil-m-38510/210e 25 device type 02 circuit g figure 3. functional block diagrams ? continued.
mil-m-38510/210e 26 device types 02 and 04 circuit h figure 3. functional block diagram ? continued.
mil-m-38510/210e 27 device type 02 circuit j figure 3. functional block diagrams ? continued.
mil-m-38510/210e 28 device types 01, 02, 03, and 04 notes: 1. test table for devices programmed in accordance with an al tered item drawing may be replaced by the equivalent tests which apply to the specific progra m configuration for the resulting read-only memory 2. c l = 30 pf minimum, including jig and probe capacitance, r 1 =330 ? 25%, and r 2 = 680 ? 20%. 3. outputs may be under load simultaneously. figure 4. switching time test circuit .
mil-m-38510/210e 29 device type 05 notes: 1. test table for devices programmed in accordance with an al tered item drawing may be replaced by the equivalent tests which apply to the specific progra m configuration for the resulting read-only memory 2. c l = 30 pf minimum, including jig and probe capacitance, r 1 =330 ? 25%, and r 2 = 680 ? 20%. 3. outputs may be under load simultaneously. figure 4. switching time test circuit ? continued.
mil-m-38510/210e 30 note: 1. all other waveform characteristics shall be as specified in table iva. figure 5a. programming voltage waveforms during programming for circuit a .
mil-m-38510/210e 31 figure 5b. programming voltage waveforms during programming for circuit b . note: all other waveforms characteristi cs shall be as specified in table ivc. figure 5c. programming voltage waveforms during programming for circuit c, device types 02 and 04.
mil-m-38510/210e 32 *current clamp or voltage clamp will be needed. figure 5c. programming voltage waveforms during programming for circuit c, device type 05 - continued.
mil-m-38510/210e 33 figure 5d. programming voltage waveforms during programming for circuit d .
mil-m-38510/210e 34 figure 5e. programming waveforms for circuit e have been discontinued . notes: 1. output load is 0.2 ma and 12 ma during 7.0 v and 4.0 v check, respectively. 2. all other wavefo rm characteristics shall be as specified in table ivf. figure 5f programming voltage waveforms during programming for circuit f.
mil-m-38510/210e 35 figure 5g. programming voltage waveforms during programming for circuit g.
mil-m-38510/210e 36 figure 5h. programming voltage waveforms during programming for circuit h.
mil-m-38510/210e 37 notes: 1. all delays between edges are specified from completion of the first edge, not midpoints. 2. delays t 1 , t 2 , t 3 , and t 4 must be greater than 100 ns; maximum delays of 1 s are recommended to minimize heating during programming. 3. during t v the output being programmed is swit ched to the load r and verified. 4. outputs not being programmed are connected to v onp through resistor which provides output current limiting. figure 5i. programming voltage waveforms during programming for circuit i .
mil-m-38510/210e 38 figure 5j. programming voltage waveforms during programming for circuit j .
table iii. group a inspection for device types 01 and 03 . terminal conditions: (outputs not designated are open or resistive coupled to gnd or voltage. inputs not designated are high 2.0 v or 0.8 v. cases j,k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 test limits subgroup symbol mil- std- 883 method test no. a7 a6 a5 a4 a3 a2 a1 a0 01 02 03 gnd 04 05 06 07 08 ce 3 ce 2 ce 1 a10 a9 a8 v cc measured terminal min max unit v ic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -10ma -10ma -10ma -10ma -10ma -10ma -10ma -10ma gnd ? ? ? ? ? ? ? ? ? ? ? ? ? -10ma -10ma -10ma -10ma -10ma -10ma 4.5v ? ? ? ? ? ? ? ? ? ? ? ? ? a7 a6 a5 a4 a3 a2 a1 a0 ce 3 ce 2 ce 1 a10 a9 a8 -1.5 ? ? ? ? ? ? ? ? ? ? ? ? ? v ? ? ? ? ? ? ? ? ? ? ? ? ? v ol 3007 ? ? ? ? ? ? ? 15 16 17 18 19 20 21 22 1 / 2 / ? ? ? ? ? ? ? 1 / 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 3 / 3 / 3 / ? ? ? ? ? ? ? ? 3 / 3 / 3 / 3 / 3 / 2.0v ? ? ? ? ? ? ? 2.0v ? ? ? ? ? ? ? 0.8v ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 01 02 03 04 05 06 07 08 0.5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i il 3009 ? ? ? ? ? ? ? ? ? ? ? ? ? 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? a7 a6 a5 a4 a3 a2 a1 a0 ce 3 ce 2 ce 1 a10 a9 a8 -1.0 ? ? ? ? ? ? ? ? ? ? ? ? ? -250 ? ? ? ? ? ? ? ? ? ? ? ? ? a ? ? ? ? ? ? ? ? ? ? ? ? ? i ih 3010 ? ? ? ? ? ? ? ? ? ? ? ? ? 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? a7 a6 a5 a4 a3 a2 a1 a0 ce 3 ce 2 ce 1 a10 a9 a8 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i cex 51 52 53 54 55 56 57 58 5.2v 5.2v 5.2v ? ? ? ? ? ? ? ? 5.2v 5.2v 5.2v 5.2v 5.2v 0.5v 0.5v 4.5v ? ? ? ? ? ? ? ? 01 02 03 04 05 06 07 08 100 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 1 t c =+25 c i cc 3005 59 gnd gnd gnd gnd gnd gnd gnd gnd ? gnd gnd gnd gnd ? v cc 185 ma see footnotes at end of table. 39 mil-m-38510/210e
table iii. group a inspection for device types 01 and 03 ? continued. terminal conditions: (outputs not designated are open or resistive coupled to gnd or voltage. inputs not designated are high 2.0 v or 0.8 v. cases j,k 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 test limits subgroup symbol mil- std- 883 method test no. a7 a6 a5 a4 a3 a2 a1 a0 01 02 03 gnd 04 05 06 07 08 ce 3 ce 2 ce 1 a10 a9 a8 v cc measured terminal min max unit 2 same tests, terminal conditions, and limits as for subgroup 1, except t c = +125 c. 3 same tests, terminal conditions, and limits as for subgroup 1, except t c = -55 c. 7 t c =+25 c funct- ional tests 4 / 60 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / gnd 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / outputs 4 / 8 same tests, terminal conditions, and limits as for subgroup 7, except t c = +125 c and -55 c. 9 t c =+25 c t phl1 t plh1 t phl2 t plh2 galpat fig. 4 sequen- tial fig. 4 61 62 63 64 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? gnd ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 5.5v 5.5v 8 / 8 / 5.5v 5.5v 8 / 8 / gnd gnd 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / outputs ? ? ? 7 / 7 / 9 / 9 / ns ? ? ? 10 same tests, terminal conditions, and limits as for subgroup 9, except t c = +125 c 11 same tests, terminal conditions, and limits as for subgroup 10, except t c = -55 c see footnotes at end of table. mil-m-38510/210e 40
table iii. group a inspection for device types 02 and 04 . outputs not designated are open or re sistive coupled to gnd or voltage. terminal conditions: inputs not designated are high 2.0 v or 0.8 v. case 3 2 3 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 22 23 24 25 26 27 28 cases j,k,l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 test limits subgroup symbol mil- std- 883 method test no. a7 a6 a5 a4 a3 a2 a1 a0 o1 o2 o3 gnd o4 o5 o6 o7 o8 ce 3 ce 2 ce 1 a10 a9 a8 v cc measured terminal min max unit v ic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -10ma -10ma -10ma -10ma -10ma -10ma -10ma -10ma gnd ? ? ? ? ? ? ? ? ? ? ? ? ? -10ma -10ma -10ma -10ma -10ma -10ma 4.5v ? ? ? ? ? ? ? ? ? ? ? ? ? a7 a6 a5 a4 a3 a2 a1 a0 ce 3 ce 2 ce 1 a10 a9 a8 -1.5 ? ? ? ? ? ? ? ? ? ? ? ? ? v ? ? ? ? ? ? ? ? ? ? ? ? ? v ol 3007 ? ? ? ? ? ? ? 15 16 17 18 19 20 21 22 1 / 2 / ? ? ? ? ? ? ? 1 / 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / 13 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 3 / 3 / 3 / ? ? ? ? ? ? ? ? 3 / 3 / 3 / 3 / 3 / 2.0v ? ? ? ? ? ? ? 2.0v ? ? ? ? ? ? ? 0.8v ? ? ? ? ? ? ? 2 / 13 / ? ? ? ? ? ? ? 2 / ? ? ? ? ? ? ? 2 / 13 / ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? o1 o2 o3 o4 o5 o6 o7 o8 0.5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? v oh 3006 ? ? ? ? ? ? ? 23 24 25 26 27 28 29 30 2 / 14 / 15 / 16 / 17 / ? ? ? ? ? 2 / 12 / 15 / 16 / 17 / ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / 18 / ? ? ? ? ? -2ma -2ma -2ma ? ? ? ? ? ? ? ? -2ma -2ma -2ma -2ma -2ma ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? ? ? ? ? ? ? ? ? o1 o2 o3 o4 o5 o6 o7 o8 2.4 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i il 3009 ? ? ? ? ? ? ? ? ? ? ? ? ? 31 32 33 34 35 36 37 38 39 40 41 42 43 44 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? a7 a6 a5 a4 a3 a2 a1 a0 ce 3 ce 2 ce 1 a10 a9 a8 -1.0 ? ? ? ? ? ? ? ? ? ? ? ? ? -250 ? ? ? ? ? ? ? ? ? ? ? ? ? a ? ? ? ? ? ? ? ? ? ? ? ? ? 1 t c =+25 c i ih 3010 ? ? ? ? ? ? ? ? ? ? ? ? ? 45 46 47 48 49 50 51 52 53 54 55 56 57 58 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? a7 a6 a5 a4 a3 a2 a1 a0 ce 3 ce 2 ce 1 a10 a9 a8 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? see footnotes at end of table. 41 mil-m-38510/210e
table iii. group a inspection for device types 02 and 04 ? continued. outputs not designated are open or re sistive coupled to gnd or voltage. terminal conditions: inputs not designated are high 2.0 v or 0.8 v. case 3 2 3 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 22 23 24 25 26 27 28 cases j,k,l 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 test limits subgroup symbol mil- std- 883 method test no. a7 a6 a5 a4 a3 a2 a1 a0 o1 o2 o3 gnd o4 o5 o6 o7 o8 ce3 ce2 ce 1 a10 a9 a8 v cc measured terminal min max unit i ohz 59 60 61 62 63 64 65 66 5.2v 5.2v 5.2v gnd ? ? ? ? ? ? ? 5.2v 5.2v 5.2v 5.2v 5.2v 0.5v ? ? ? ? ? ? ? 0.5v ? ? ? ? ? ? ? 4.5v ? ? ? ? ? ? ? 5.5v ? ? ? ? ? ? ? o1 o2 o3 o4 o5 o6 o7 o8 100 ? ? ? ? ? ? ? a ? ? ? ? ? ? ? i olz 67 68 69 70 71 72 73 74 0.5v 0.5v 0.5v ? ? ? ? ? ? ? ? 0.5v 0.5v 0.5v 0.5v 0.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? o1 o2 o3 o4 o5 o6 o7 o8 -100 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? i os 3011 ? ? ? ? ? ? ? 75 76 77 78 79 80 81 82 14 / 2 / 15 / 16 / 17 / ? ? ? ? ? 2 / 15 / 12 / 16 / 17 / ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 17 / 2 / 15 / 16 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 18 / 2 / 15 / 16 / 17 / ? ? ? ? ? gnd gnd gnd ? ? ? ? ? ? ? ? gnd gnd gnd gnd gnd 4.5v ? ? ? ? ? ? ? 4.5v ? ? ? ? ? ? ? 0.5v ? ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? 2 / 15 / 16 / 17 / ? ? ? ? ? ? ? ? ? ? ? ? ? ? o1 o2 o3 o4 o5 o6 o7 o8 -10 ? ? ? ? ? ? ? -100 ? ? ? ? ? ? ? ma ? ? ? ? ? ? ? 1 t c =+25 c i cc 3005 83 gnd gnd gnd gnd gnd gnd gnd gnd ? gnd gnd gnd gnd ? v cc 185 ? 2 same tests, terminal conditions, and limits as for subgroup 1, except t c = +125 c. 3 same tests, terminal conditions, and limits as for subgroup 1, except t c = -55 c. 7 t c =+25 c funct- ional tests 4 / 84 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / gnd 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / outputs 4 / 8 same tests, terminal conditions, and limits as for subgroup 7, except tc = +125 c and -55 c. 9 t c =+25 c t phl1 t plh1 t phl2 t plh2 galpat fig. 4 sequen- tial fig. 4 85 86 87 88 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? gnd ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 5.5v 5.5v 8 / 8 / 5.5v 5.5v 8 / 8 / gnd gnd 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / outputs ? ? ? 7 / 7 / 9 / 9 / ns ? ? ? 10 same tests, terminal conditions, and limits as for subgroup 9, except t c = +125 c. 11 same tests, terminal conditions, and limits as for subgroup 10, except t c = -55 c. see footnotes at end of table. 42 mil-m-38510/210e
table iii. group a inspection for device type 05 . outputs not designated are open or re sistive coupled to gnd or voltage. terminal conditions: inputs not designated are high 2.0 v or 0.8 v. case r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test limits subgroup symbol mil- std- 883 method test no. a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd o4 o3 o2 o1 ce 2 ce 1 a11 a10 a9 v cc measured terminal min max unit v ic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 -10ma -10ma -10ma -10ma -10ma -10ma -10ma -10ma -10ma gnd ? ? ? ? ? ? ? ? ? ? ? ? ? -10ma -10ma -10ma -10ma -10ma 4.5v ? ? ? ? ? ? ? ? ? ? ? ? ? a8 a7 a6 a5 a4 a3 a2 a1 a0 ce 2 ce 1 a11 a10 a9 -1.5 ? ? ? ? ? ? ? ? ? ? ? ? ? v ? ? ? ? ? ? ? ? ? ? ? ? ? v ol 3007 ? ? ? 15 16 17 18 1 / 2 / ? ? ? 2 / ? ? ? 2 / 19 / ? ? ? 2 / 19 / ? ? ? 2 / 19 / ? ? ? 2 / 19 / ? ? ? 2 / 19 / ? ? ? 2 / 19 / ? ? ? 2 / 19 / ? ? ? ? ? ? ? 3 / 3 / 3 / 3 / 0.8v ? ? ? 0.8v ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? ? ? ? ? o4 o3 o2 o1 0.5 ? ? ? ? ? ? ? v oh 3006 ? ? ? 19 20 21 22 2 / ? ? ? ? ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? ? ? ? ? -2ma -2ma -2ma -2ma ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? o4 o3 o2 o1 2.4 ? ? ? ? ? ? ? i il 3009 ? ? ? ? ? ? ? ? ? ? ? ? ? 23 24 25 26 27 28 29 30 31 32 33 34 35 36 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v 0.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0.5v 0.5v 0.5v 0.5v 0.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? a8 a7 a6 a5 a4 a3 a2 a1 a0 ce 2 ce 1 a11 a10 a9 -1.0 ? ? ? ? ? ? ? ? ? ? ? ? ? -250 ? ? ? ? ? ? ? ? ? ? ? ? ? a ? ? ? ? ? ? ? ? ? ? ? ? ? 1 t c =+25 c i ih 3010 ? ? ? ? ? ? ? ? ? ? ? ? ? 37 38 39 40 41 42 43 44 45 46 47 48 49 50 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? 5.5v 5.5v 5.5v 5.5v 5.5v ? ? ? ? ? ? ? ? ? ? ? ? ? ? a8 a7 a6 a5 a4 a3 a2 a1 a0 ce 2 ce 1 a11 a10 a9 50 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? see footnotes at end of table. 43 mil-m-38510/210e
table iii. group a inspection for device type 05 ? continued. outputs not designated are open or re sistive coupled to gnd or voltage. terminal conditions: inputs not designated are high 2.0 v or 0.8 v. case r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test limits subgroup symbol mil- std-883 method test no. a8 a7 a6 a5 a4 a3 a2 a1 a0 gnd o4 o3 o2 o1 ce 2 ce 1 a11 a10 a9 v cc measured terminal min max unit i ohz 51 52 53 54 gnd ? ? ? 5.2v 5.2v 5.2v 5.2v 4.5v ? ? ? 4.5v ? ? ? 5.5v ? ? ? o4 o3 o2 o1 100 ? ? ? a ? ? ? i olz 55 56 57 58 ? ? ? ? 0.5v 0.5v 0.5v 0.5v ? ? ? ? ? ? ? ? ? ? o4 o3 o2 o1 -100 ? ? ? ? ? ? ? i os 3011 ? ? ? 59 60 61 62 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? ? ? ? ? gnd gnd gnd gnd 0.5v ? ? ? 0.5v ? ? ? 2 / ? ? ? 2 / ? ? ? 2 / ? ? ? ? ? ? ? o4 o3 o2 o1 -10 ? ? ? -100 ? ? ? ma ? ? ? 1 t c =+25 c i cc 3005 63 gnd gnd gnd gnd gnd gnd gnd gnd gnd ? gnd gnd gnd gnd gnd ? v cc 185 ? 2 same tests, terminal conditions, and limits as for subgroup 1, except t c = +125 c. 3 same tests, terminal conditions, and limits as for subgroup 1, except t c = -55 c. 7 t c =+25 c funct- ional tests 4 / 64 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / gnd 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / 4 / outputs 4 / 8 same tests, terminal conditions, and limits as for subgroup 7, except t c = +125 c and t c = -55 c. 9 t c =+25 c t phl1 t plh1 t phl2 t plh2 galpat fig. 4 sequen- tial fig. 4 65 66 67 68 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / gnd ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? 6 / ? ? ? gnd gnd 8 / 8 / gnd gnd 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / 5 / 5 / 8 / 8 / outputs ? ? ? 80 80 40 40 ns ? ? ? 10 same tests, terminal conditions, and limits as for subgroup 9, except t c = +125 c. 11 same tests, terminal conditions, and limits as for subgroup 9, except t c = -55 c. 44 mil-m-38510/210e
mil-m-38510/210e 45 1 / for unprogrammed devices, apply 13.0 v on pin 1(a7) and pin 2 (a6), for device types 01 and 02, and on pin 1 (a8) for device type 05 for circuit a devices. 2 / for programmed devices, select an appropriate addr ess to acquire the desir ed output state. v ih = 2.0 v, v il = 0.8 v. 3 / i ol = 8 ma for circuits c and g. i ol = 16 ma for circuits a, b, d, f, h, i, and j. 4 / the functional tests shall verify that no fuses are blown fo r unprogrammed devices or that the altered item drawing pattern exists for programmed devices (see table ii and 3. 3.2.1). all bits shall be tested. terminal conditions shall be as follows: a. inputs: h = 2.4 v, l = 0.4 v b. outputs: output voltage shall be: h 1.5 v and l 1.5 v. c. the functional tests shall be performed with v cc = 4.5 v and v cc = 5.5 v. 5 / galpat (programmed prom). this program will test all bits in the array, the addressing and interaction between bits for ac performance, t phl1 and t plh1 . each bit in the pattern is fixed by bei ng programmed with an ?h? or ?l?. description : 1. word 0 is read. 2. word 1 is read. 3. word 0 is read. 4. word 2 is read. 5. word 0 is read. 6. the reading procedure contin ues back and forth between word 0 and the next higher numbered word until word 2047 or 4095 is reached, then increments to the next word and reads back and forth as in step 1 through 7 and shall include all words. 7. pass execution time = (n 2 + n) x cycle time. n = 2048 or 4096. 8. the galpat tests shall be performed with v cc = 4.5 v and 5.5 v. 6 / the outputs are loaded per figure 4. 7 / t phl1 , t plh1 = 100 ns for device types 01 and 02 and 55 ns for device types 03 and 04. 8 / sequential test (programmed prom). this pr ogram will test all bits in the array for t phl2 and t plh2 . description : 1. each word in the pattern is tested from the enable lines to the output lines for recovery. 2. word 0 is addressed. enable line is pulled hi to lo and lo to hi. t phl2 and t plh2 are read. 3. word 1 is addressed. same enable sequence as above. 4. the reading procedure continues until word 2047 or 4095 is reached. 5. pass execution time = 2048 x cycle time (or 4096 x cycle time). 6. the se quential tests shall be performed with v cc = 4.5 v and 5.5 v. 9 / t phl2 , t plh2 = 50 ns for device types 01 and 02 and 30 ns for device types 03 and 04. 10 / for uprogrammed devices, apply 13 v on pin 8 (a0) for circuit i devices. 11 / for unprogrammed devices, 12.0 v on pin 6 (a2) and 0.0 v on pin 5 (a3) for circuit f devices. 12 / for unprogrammed devices, apply 13 v on pin 2 (a6) for circuit i devices.
mil-m-38510/210e 46 13 / for unprogrammed devices, apply 10 v to pin 4 (a4), apply v oh to pin 21 (a10), and apply v ol to pin 23 (a8) for circuit h. 14 / for unprogrammed devices, apply 10.5 v on pin 1 (a7) for circuit b devices.. 15 / for unprogrammed devices, apply 10.5 v to pin 3 (a5), apply 0 v to pins 4, 5, 6, 7, 8 (a4, a3, a2, a1, a0), and apply 3 v to pins 1, 2, 21, 22, 23, (a7, a6, a10, a9, a8) for circuit g devices. 16 / for unprogrammed devices type 02 (82s191), with date codes before 8626. apply 10.0 v on pin 6 (a2); apply 5.0 v to all other addresses for circuit c devices. 17 / for unprogrammed device types 02 (with date codes 8626 or later) and 04 (82s191a), apply 10.0 v on a4; apply 5.0 v on a0, a1, a2, a3 and a6; and appl y 0.5 v on a5, a7, a8, a9 and a10 for circuit c devices. 18 / for unprogrammed devices, apply 12.0 v on pin 8 (a0) for circuit d devices. 19 / for unprogrammed device type 05, apply 15.0 v to pin 4 (a5); apply 0.0 v to pins 5, 9 (a4, a0); apply 4.5 v to pins 3, 6, 7, 8 (a6, a3, a2, a1) for circuit c devices.
mil-m-38510/210e 47 table iva. programming characteristics for circuit a. limits 1 / parameter symbol min recommended max unit address input voltage 2 / v ih v il 2.4 0.0 5.0 0.4 5.0 0.5 v v programming voltage to v cc low program verify verify voltage v ph 3 / v pl v phv v r 4 / 10.75 0.0 ---- 4.5 11.0 0.0 5.5 ---- 11.25 1.5 ---- 5.5 v ? ? ? programming input low current at v ph i ilp ---- -300 -600 a programming voltage (v cc ) transition time t tlh t thl 1 1 5 5 10 10 s s programming delay t d1 t d2 10 1 10 5 20 5 s s programming pulse width t p 5 / 90 100 110 s programming duty cycle pdc ---- 30 60 % output voltage enable disable v ope 6 / v opd 10.5 0.0 10.5 5.0 11.0 5.5 v v during the programming the chip must be disabled for proper operation. 1 / t a = +25 c. 2 / no inputs should be left open for v ih . 3 / v ph source must be capable of supplying one ampere. 4 / it is recommended that post programming dual verification be made at v min r and v max r . 5 / note step j in programming procedure. 6 / v ope source must be capable of supplying 10 ma minimum.
mil-m-38510/210e 48 table ivb. programming characteristics for circuit b. limits parameter symbol conditions 1 / min recommended max unit v cc required during programming v ccp 10.5 11.0 11.5 v vout current limit during programming i op 20 25 30 ma output programming voltage v out 10.5 11.0 11.5 v pulse width of programming voltage t p 9 10 11 s programming delay t d 0 1 10 s v ccp or v out transition time t tlh rise time of v cc or v out 1 5 10 v/ s v ccp current i ccp 800 900 1,000 ma low v cc for verification v ccl 3.9 4.0 4.1 v high v cc for verification v cch 5.8 6.0 6.2 v v ih 2.4 5.0 5.5 v address input voltage v il 0.0 0.4 0.8 v maximum duty cycle during automatic programming of program pin and output pin d.c. t p / t c ---- 25 50 % 1 / t c = +25 c.
mil-m-38510/210e 49 table ivc. programming characteristics for circuit c, device types 02 and 04. limits parameter symbol conditions 1 / min recommended max unit programming voltage to v cc v ccp 2 / i ccp = 375 75 ma transient or steady-state 8.5 8.75 9.0 v verificaiton upper limit v cch 5.3 5.5 5.7 v verificaiton lower limit v ccl 4.3 4.5 4.7 v verify threshold v s 3 / 1.4 1.5 1.6 v programming supply current i ccp v ccp = +8.75 0.25 v 300 450 ma input voltage, high level ?1? v ih 2.4 5.5 v input voltage, low level ?0? v il 0 0.4 0.8 v input current i ih v ih = +5.5 v 50 a input current i il v il = +0.4 v -500 a output programming voltage v out 4 / i out = 200 20 ma; transient or steady-state 16 17 18 v output programming current i out v out = 17 v 1 v 180 200 220 ma programming voltage transition time t tlh 10 50 s ce programming pulse width t p 300 400 500 s pulse sequence delay t d 10 s 1 / t c = +25 c. 2 / bypass v cc to gnd with a 0.01 f capacitor to reduce voltage spikes. 3 / v s is the sensing threshold of the prom output voltage for a programmed bit. it normally constitutes the reference voltage applied to a comparator ci rcuit to verify a su ccessful fusing attempt. 4 / care should be taken to insure the 17 v 1 v output voltage is maintained dur ing the entire fusing cycle. the recommended supply is a constant current sour ce clamped at the s pecified voltage limit.
mil-m-38510/210e 50 table ivc. programming characteristics for circuit c, device type 05 ? continued. limits parameter symbol conditions 1 / min recommended max unit programming voltage to v cc 2 / v ccp i ccp = 425 75 ma transient or steady-state 8.5 8.75 9.0 v verify voltage v ccv 4.75 5.0 5.25 v input voltage, high level ?1? v ih i ih = 50 a 2.4 3.0 5.5 v input voltage, low level ?0? v il i il = 500 a 0.0 0.0 0.5 v forced output current i opf v opf = 17.5 0.5 v 150 185 220 ma forced output voltage (program) 3 / v opf1 i opf = 300 25 ma 17.0 17.5 18.0 v forced output voltage (program) 3 / v opf2 i opf = 300 25 ma 20.0 22.0 v output voltage high v oh 2.4 5.25 v output voltage low v ol 0.0 0.45 v v cc delay time t d1 50% to 10% v ccp 10 10 25 s v out delay time t d2 90% v ccp to 10% v off 1.0 1.0 5.0 s pulse sequence delays t d3 ? t d8 see figure 5c 1.0 1.0 10 s v cc rise time t r1 0 % to 100% 4.0 7.0 8.0 s v out rise time t r2 10% to 90% 3.0 10 17 s v cc fall time t f1 100% to 0% 2.0 4.0 10 s v out fall time t f2 100% to 0% 4.0 7.0 20 s ce 2 programming pulse width 4 / t p 10% to 10% 5.0 10 30 s ce 2 verify pulse width 4 / t v 10% to 10% 5.0 5.0 10 s clock pulse width (ck) t wc 50% to 50% 0.5 0.75 1.0 s 1 / t c = +25 c. 2 / if the overall program/verify cycle exceeds the re commended value, a 25% duty cycle must be used for v ccp . 3 / v opf supply should regulate to 0.25 v at i opf . maximum slew rate for v opf should be 1.0 v/ s. 4 / ce 2 rise time slew rate should be 1.0 v/ns maximum. ce 2 fall time slew rate should be 10.0 v/ns maximum.
mil-m-38510/210e 51 table ivd. programming characteristics for circuit d. limits parameter symbol conditions 1 / min recommended max unit power supply voltage v cc 6.4 6.5 6.6 v power supply rise time 2 / t r(vcc) 0.2 2.0 s power supply fall time 2 / t f(vcc) 0.2 2.0 s v cc on time 3 / t on see programming v cc off time 4 / t off time diagram duty cycle for v cc t on /( t off + t on ) 50 % read delay before programming t drbp initial check 3.0 s fuse read time t w 5 / 1.0 s delay to v cc off t d(vcc) 5 / 1.0 s delay to read after programming t drap 5 / programming verification 3.0 s chip select programming voltage v csp 20.0 20.0 22.0 v chip select program current limit i csp 175 180 185 ma input voltage low v il 0.0 0.0 0.4 v input voltage high v ih 2.4 5.0 5.0 v delay to chip deselect t dcs 1.0 s chip select pulse rise time t rcs 3.0 4.0 s delay to chip select time t dap 0.2 1.0 s chip select pulse fall time t fcs 0.1 0.1 1.0 s see footnotes at end of table.
mil-m-38510/210e 52 table ivd. programming characteristics for circuit d ? continued. ramp characteristics limits parameter symbol conditions 1 / min recommended max unit programming current linear point i oplp 10 20 ma output programming current limits i op(max) apply current ramp to selected output 155 160 165 ma output programming voltage limit v op(max) 24 25 26 v current slew rate sr iop constant after linear point 0.9 1.0 1.1 ma/ s blow sense voltage v ps 0.7 v delay to programming ramp t dbp 2.0 3.0 s time to reach linear point t lp 0.2 1.0 10 s program sense inhibit t ss 2.0 3.0 10 s time to program fuse t tp 3.0 150 s programming ramp hold time t hap after fuse programs 1.4 1.5 1.6 s programming ramp fall time 2 / t fiop 0.1 0.2 s 1 / t c = +25 c 2 / rise and fall times are from 10% to 90%. 3 / total time v cc is on to program fuse is equal to or greater than the sum of all the specified delays, pulse widths and rise/fall times. 4 / t off is equal to or greater than t on . 5 / proceed to next address after read strobe indicates programmed cell. table ive. programming characteristics for circuit e ? discontinued.
mil-m-38510/210e 53 table ivf. programming characteristics for circuit f . limits parameter symbol conditions 1 / min recommended max unit v cc required during programming v ccp 5.4 5.5 5.6 v rise time of program pulse to data out or program pin t tlh 0.34 0.40 0.46 v/ s programming voltage on program pin v pp 32.5 33 33.5 v output programming voltage v out 25.5 26 26.5 v programming pin pulse width ( ce ) t pp chip disabled, v cc = 5.5 v ---- 100 180 s pulse width of programming voltage t p 1 40 s required current limit of power supply feeding program pin and output during program i l v pp = 33 v, v out = 26 v, v cc = 5.5 v 240 ---- ma required time delay between disabling memory output and application of output programming pulse t d1 measured at 10% levels 70 80 90 s required time delay between removal of programming pulse and enabling memory output t d2 100 ns output current during verification i olv1 chip enabled, v cc = 4.0 v 11 12 13 ma i olv2 chip enabled, v cc = 7.0 v 0.19 0.2 0.21 ma address input voltage v ih 2.4 5.0 5.5 v v il 0.0 0.4 0.8 v maximum duty cycle during automatic programming of program pin and output pin d.c. t p /t c ---- ---- 25 % 1 / t c = 25 c
mil-m-38510/210e 54 table ivg. programming char acteristics for circuit g . limits parameter symbol conditions 1 / min recommended max unit required v cc for programming v ccp 10.0 10.5 11.0 v i cc during programming i ccp v cc = 11 v 750 ma required output voltage for programming v op 10.0 10.5 11.0 v output current while programming i op v out = 11 v 20 ma rate of voltage change of v cc or output i rr 1.0 10.0 v/ s programming pulse width (enabled) pwe 9 10 11 s required v cc for verification v ccv 3.8 4.0 4.2 v maximum duty cycle for v cc at v ccp mdc 25 25 % address set-up time t 1 100 ns v ccp set-up time t 2 2 / 5 s v ccp hold time t 5 100 ns v op set-up time t 3 100 ns v op hold time t 4 100 ns 1 / t c = +25 c. 2 / v ccp setup time may be greater than 0 if v ccp rises at the same rate or faster than v op .
mil-m-38510/210e 55 table ivh. programming characteristics for circuit h . 1 / parameters symbol min nom max unit steady-state supply voltage v cc 4.75 5 5.25 v input voltage v ih 3 4 5 v v il 0 0 0.5 v voltage all outputs except the one to be programmed 0 0 0.5 v supply voltage level to program a bit v cc(pr) 5.75 6 6.25 v select or enable level to program a bit v s(pr) 9.75 10 11 v output level during interval t5 v o(pr) 15.75 16 16.25 v supply voltage during verification (see step 0) low 4.4 4.5 4.6 v high 5.4 5.5 5.6 v time for v cc to settle and to verify need to program t 1 0 5 10 s timing from v cc = 6 v until chip select (enable) is at 10 v t 2 5 5 10 s timing from chip select (enable) high to start or program ramp t 3 0.1 5 10 s ramp time, output program pulse t 4 10 15 20 s duration of output program pulse t 5 15 20 20 s time from end of program pulse to chip select (enable) low t 6 5 5 10 s time from chip select (enable) low to v cc = 0 v t 7 0.1 5 5 s time for cooling between bits t 8 30 50 100 s time for cooling between words t 9 30 50 s 1 / t c = +25 c.
mil-m-38510/210e 56 table ivi. programming char acteristics for circuit i . limits parameter symbol conditions 1 / min recommended max unit v cc during programming v ccp 5.0 5.5 v high level input voltage during programming v ihp 2.4 5.5 v low level input voltage during programming v ilp 0.0 0.45 v chip enable voltage during programming v cep ce 1 pin 14.5 15.5 v output voltage during programming v op 19.5 20.5 v voltage on outputs not to be programmed v onp 0 v ccp + 0.3 v current on outputs not to be programmed i onp 20 ma rate of output voltage change d(v op )/dt 20 250 v/ s rate of chip enable voltage change d(v ce )/dt ce 1 pin 100 1000 v/ s programming period tp 50 100 s v cc during programming verification v ccl 4.5 5.0 s 1 / t c = +25 c.
mil-m-38510/210e 57 table ivj. programming characteristics for circuit j . limits 1 / parameters symbol min recomme nded max unit address input voltage 2 / v ih 2.4 5.0 5.0 v vil 0.0 0.4 0.8 v programming/verify voltage to v cc v ph 11.75 12.0 12.25 v v pl 4.5 4.5 5.5 v programming voltage current limit with v ph applied i ccp 600 600 650 ma voltage rise and fall time t r 1.0 1.0 10 s t f 1.0 1.0 10 s programming delay t d 10 10 100 s programming pulse width t p 100 1000 s programming duty cycle dc ---- 50 90 % output voltage enable v ope 10.0 10.5 11.0 v output voltage disable 3 / v opd 4.5 5.0 5.5 v 1 / t c = +25 c. 2 / address and chip select shall not be left open for v ih . 3 / disable condition shall be met with output open circuit.
mil-m-38510/210e 58 5. packaging 5.1 packaging requirements. for acquisition purposes, the packaging re quirements shall be as specified in the contract or order (see 6.2). when packaging of materiel is to be performed by dod or in-house contractor personnel, these personnel need to contact the responsible packaging activity to ascertain packaging requirements. packaging requirements are maintained by the inventory control point' s packaging activity within the military service or defense agency, or within the military service' s system command. packaging data retrieval is available from the managing military department's or defense agency's automated pa ckaging files, cd-rom products, or by contacting the responsible packaging activity. 6. notes (this section contains information of a general or explanatory nature which may be helpful, but is not mandatory.) 6.1 intended use. microcircuits conforming to this specificati on are intended for logistic support of existing equipment. 6.2 acquisition requirements. acquisition documents should specify the following: a. title, number, and date of the specification. b. pin and compliance identifier, if applicable (see 1.2). c. requirements for delivery of o ne copy of the conformance inspection data pertinent to the device inspection lot to be supplied with each shipment by the device manufacturer, if applicable. d. requirements for certificate of compliance, if applicable. e. requirements for notification of change of product or process to contracting activity in addition to notification to the qualifyi ng activity, if applicable. f. requirements for failure analysis (including requ ired test condition of method 5003 of mil-std-883), corrective action, and reporting of results, if applicable. g. requirements for product assurance options. h. requirements for special lead lengths, or lead forming, if applicable. unless otherwise specified, these requirements will not apply to direct purchase by or direct shipment to the government. i. requirement for programming the device, includi ng processing option. the device may be programmed pre- or post-burn-in, if applicable. j. requirements for "jan" marking. k. packaging requirements (see 5.1) 6.3 qualification . with respect to products requiring qualification, awards will be made only for products which are, at the time of award of contrac t, qualified for inclusion in qualified manu facturers list qml-38535 whether or not such products have actually been so listed by that date. the attention of the cont ractors is called to these requirements, and manufacturers are urged to arrange to have the products that they propose to offer to the federal government tested for qualification in order that they may be eligible to be awarded contracts or purchase orders for the products covered by this specification. information pertaining to qualification of products may be obtained from dscc-vq, 3990 e. broad street, columbus, ohio 43218-3990.
mil-m-38510/210e 59 6.4 superseding information . the requirements of mil-m-38510 have be en superseded to take advantage of the available qualified manufacturer listing (qml) system pr ovided by mil-prf-38535. previous references to mil-m- 38510 in this document have been replaced by appropriate re ferences to mil-prf-38535. all technical requirements now consist of this specification and mil-prf-38535. the mil-m-38510 spec ification sheet number and pin have been retained to avoid adversely impacting existing govern ment logistics systems and contractor's parts lists. 6.5 abbreviations, symbols, and definitions. the abbreviations, symbols, and definitions used herein are defined in mil-prf-38535, mil-hdbk-1331, and as follows: gnd ............................................ ground zero voltage potential. v in ............................................... volt age level at an input terminal v ic ................................................ input cl amp voltage i in ................................................. current fl owing into an input terminal 6.6 logistic support. lead materials and finishes (see 3.4) are in terchangeable. unless otherwise specified, microcircuits acquired for government logistic support will be acquired to device class b (see 1.2.2), lead material and finish c (see 3.4). longer length leads and lead forming sh ould not affect the part number. it is intended that spare devices for logistic support be acquired in the unprogrammed condition (see 3.8.1) and programmed by the maintenance activity, except where use quantities for devices with a specific program or pattern justify stocking of preprogrammed devices. 6.7 substitutability. the cross-reference information below is presented for the convenience of users. microcircuits covered by this specification will functionally replace the listed generic-industry type. generic-industry microcircuit types may not have equivalent operational performance characteristics across military temperature ranges or reliability factors equivalent to mil-m-38510 device types and may have slig ht physical variations in relation to case size. the presence of this information should not be deemed as permitting substitution of generic-industry types for mil-m-38510 types or as a waiver of any of the provisions of mil-prf-38535. military device type generic-industry type circuit designator fusible links cage number 01 1 / 76160 / harris a nicr 34371 01 1 / 53s1680/monolithic memories b tiw 50364 01 1 / 82s190/signetics corp. c nicr 18324 01 1 / 77s190/national g tiw/w 27014 02 1 / 76161/harris a nicr 34371 02 1 / 53s1681 / monolithic memories b tiw 50364 02, 04 82s191a/signetics corp. c nicr 18324 02 1 / 3636/intel e polysilicon 34649 02 1 / 29681/raytheon f nicr 07933 02 1 / 77s191/national g tiw/w 27014 02, 04 1 / 28s166a/texas instruments h tiw 01295 02 1 / 27s191/advanced micro devices i platinum silicide 34335 02 1 / 76161/motorola j nicr 04713 03 1 / 93z510/fairchild d zve 2 / 07263 04, 02 1 / 93z511/fairchild d zve 07263 05 1 / 76165/harris a nicr 34371 05 1/ 82hs195/signetics corp. c zve 18324 1 / this generic-industry type is no longer manufactured. 2 / zapped vertical emitter.
mil-m-38510/210e 60 6.8 change from previous issue. marginal notations are not used in this re vision to identify chang es with respect to the previous issue, due to the extensiveness of the changes. custodians: preparing activity: army - cr dla - cc navy - ec air force - 11 dla - cc review activities: (project 5962-2006-003) army ? sm, mi navy - as, cg, mc, sh td air force ? 03, 19, 99 note: the activities listed above were interested in th is document as of the date of this document. since organization and responsibilities can change, you should veri fy the currency of the info rmation above using the assist online database at http://assist.daps.dla.mil.

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